The escalating demands for high density and performance associated with non-volatile memory devices, such as electrically erasable programmable read only memory (EEPROM) devices, require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology. For example, the reduction of design features makes it difficult for the memory device to meet its expected data retention requirement.
One particular problem with non-volatile memory devices involves reactions between the control gate and an inter-gate dielectric formed between the control gate and a charge storage element. For example, reactions at the interface between the control gate and an inter-gate dielectric, including inter-gate dielectrics having a high dielectric constant (K) value, have been shown to result in modification of the work function of the control gate. The reactions between the control gate and the inter-gate dielectric may also result in dopant diffusion from the control gate into other layers and degradation of the inter-gate dielectric. These problems may make it difficult for the memory device to be efficiently programmed and/or erased. In addition, these problems may make it difficult for the memory device to meet the expected data retention requirement and, ultimately, may lead to device failure.